1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to various methods of recessing an active region and adjacent isolation structures in a common etch process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. These transistors are typically electrically separated by an isolation region, such as a shallow trench isolation (STI) region, that may be fabricated using known techniques.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form such integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. One problem that arises with current processing techniques is that, after the STI regions are formed, at least portions of the STI regions are exposed to many subsequent etching or cleaning processes that tend to consume, at least to some degree, portions of the STI structures subjected to such etching processes. As a result, the STI structures may not perform their isolation function as intended, which may result in problems such as increased leakage currents, etc. Furthermore, since the erosion of the STI structures is not uniform across a die or a wafer, such structures may have differing heights, which can lead to problems in subsequent processing operations. For example, such height differences may lead to uneven surfaces on subsequently deposited layers of material, which may require additional polishing time in an attempt to planarize the surface of such layers. Such additional polishing may lead to the formation of additional particle defects, which may reduce device yields.
Additionally, a PFET transistor is typically provided with a so-called channel layer of epitaxial silicon/germanium to improve the performance of the PFET transistor. This channel layer of silicon/germanium is typically not present on an NFET transistor. Thus, it is common practice to perform an etching process to recess the P-active region of the substrate, while masking the N-active region of the substrate, such that, when the channel layer of epitaxial silicon/germanium is formed, the upper surface of the substrate in the N-active region will be approximately level with the upper surface of the channel layer of epitaxial silicon/germanium in the P-active region of the substrate.
Various techniques have been employed to attempt to minimize topography differences between PFET and NFET devices and adjacent isolation regions. In one technique, with the NFET masked with a photoresist mask, an initial isotropic wet etching process, using for example HF acid, is performed to reduce the thickness of the isolation structures adjacent the P-active region by about 10 nm or so. This wet etching process also removes some of the isolation material from under the photoresist mask due to the isotropic nature of the etching process. Thereafter, the photoresist mask is removed, and a layer of epitaxial silicon/germanium is formed selectively on the P-active region. A hard mask layer, such as a silicon dioxide hard mask, positioned on the N-active region prevents the formation of the silicon/germanium material on the N-active region during this process. The etch rate of the isolation material during this wet etching process also varies depending upon how close adjacent transistors are positioned relative to one another. In general, the etching rate of the isolation material is greater the more closely spaced are the transistors. The space-dependency variation in the etch rate of the isolation material can also lead to undesirable height differences in the various isolation structures formed in a substrate. Another problem associated with this technique is that the photoresist mask must be removed from above the N-active region prior to forming the epitaxial channel layer of silicon/germanium. That is why the hard mask layer is also positioned above the N-active region—to prevent the formation of silicon/germanium material on the N-active region. However, in the case where the silicon recess is performed in situ, the recessed silicon surface in the P-active region is not subjected to a general cleaning process, such as an HF cleaning process, for fear of removing the protective hard mask layer in the N-active region.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.